From 36137438446c1754a522c5b3cc3aff92c43ac1ee Mon Sep 17 00:00:00 2001 From: Aleksa Vuckovic Date: Wed, 13 Dec 2023 01:38:14 +0100 Subject: Initial commit X86/X86_64 debug/release WORKING riscv64 WORKING uart idk --- src/arch/riscv64/io/uart.rs | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/arch/riscv64/io/uart.rs (limited to 'src/arch/riscv64/io/uart.rs') diff --git a/src/arch/riscv64/io/uart.rs b/src/arch/riscv64/io/uart.rs new file mode 100644 index 0000000..7aafeef --- /dev/null +++ b/src/arch/riscv64/io/uart.rs @@ -0,0 +1,27 @@ +use core::fmt; +use core::fmt::Write; + +pub fn _print(args: fmt::Arguments) { + // Not thread safe but no dependencies + let mut stdout = Stdout; + fmt::write(&mut stdout, args); +} + +struct Stdout; +impl Write for Stdout { + fn write_str(&mut self, s: &str) -> fmt::Result { + print_string(s); + Ok(()) + } +} + +pub fn print_string(s: &str) { + let uart_base = 0x10000000 as *mut u8; + while unsafe { uart_base.add(5).read_volatile() } & 0x20 == 0 {} + + for c in s.chars() { + unsafe { + uart_base.write_volatile(c as u8); + } + } +} -- cgit v1.2.3