From bd7d4366b6643b5c6cd04f40dd32f5d9c9575fd6 Mon Sep 17 00:00:00 2001 From: Aleksa Vuckovic Date: Fri, 5 Aug 2022 14:33:51 +0200 Subject: organised files; switched to recursive make --- kernel/src/cpu/idt.c | 88 ++++++++++++++ kernel/src/cpu/io.c | 13 +++ kernel/src/cpu/irq.c | 289 ++++++++++++++++++++++++++++++++++++++++++++++ kernel/src/cpu/irq_stub.S | 108 +++++++++++++++++ kernel/src/cpu/pic.c | 24 ++++ 5 files changed, 522 insertions(+) create mode 100644 kernel/src/cpu/idt.c create mode 100644 kernel/src/cpu/io.c create mode 100644 kernel/src/cpu/irq.c create mode 100644 kernel/src/cpu/irq_stub.S create mode 100644 kernel/src/cpu/pic.c (limited to 'kernel/src/cpu') diff --git a/kernel/src/cpu/idt.c b/kernel/src/cpu/idt.c new file mode 100644 index 0000000..bf285b7 --- /dev/null +++ b/kernel/src/cpu/idt.c @@ -0,0 +1,88 @@ +#include +#include +#include + +__attribute__((aligned(0x10))) static idt_entry idt_table[256]; +idtp idt_pointer; + +void load_idt(idtp* pointer) +{ + __asm__ volatile ("lidt (%0); sti;" : : "r"(pointer) : ); +} + +void add_to_idt(uint16_t num, uint64_t offset, uint16_t selector, uint8_t type) +{ + idt_table[num].offset_1 = offset & 0xFFFF; + idt_table[num].offset_2 = (offset >> 16) & 0xFFFF; + idt_table[num].offset_3 = offset >> 32; + idt_table[num].selector = selector; + idt_table[num].type_attributes = type; + idt_table[num].ist = 0; + idt_table[num].zero = 0; +} + +void init_idt_table(void) +{ + // exceptions + add_to_idt(0, (uint64_t)isr0, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(1, (uint64_t)isr1, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(2, (uint64_t)isr2, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(3, (uint64_t)isr3, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(4, (uint64_t)isr4, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(5, (uint64_t)isr5, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(6, (uint64_t)isr6, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(7, (uint64_t)isr7, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(8, (uint64_t)isr8, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(9, (uint64_t)isr9, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(10, (uint64_t)isr10, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(11, (uint64_t)isr11, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(12, (uint64_t)isr12, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(13, (uint64_t)isr13, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(14, (uint64_t)isr14, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(15, (uint64_t)isr15, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(16, (uint64_t)isr16, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(17, (uint64_t)isr17, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(18, (uint64_t)isr18, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(19, (uint64_t)isr19, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(20, (uint64_t)isr20, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(21, (uint64_t)isr21, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(22, (uint64_t)isr22, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(23, (uint64_t)isr23, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(24, (uint64_t)isr24, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(25, (uint64_t)isr25, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(26, (uint64_t)isr26, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(27, (uint64_t)isr27, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(28, (uint64_t)isr28, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(29, (uint64_t)isr29, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(30, (uint64_t)isr30, GDT_CODE_SEG, TRAP_GATE); + add_to_idt(31, (uint64_t)isr31, GDT_CODE_SEG, TRAP_GATE); + + // interrupts + add_to_idt(32, (uint64_t)irq0, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(33, (uint64_t)irq1, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(34, (uint64_t)irq2, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(35, (uint64_t)irq3, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(36, (uint64_t)irq4, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(37, (uint64_t)irq5, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(38, (uint64_t)irq6, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(39, (uint64_t)irq7, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(40, (uint64_t)irq8, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(41, (uint64_t)irq9, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(42, (uint64_t)irq10, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(43, (uint64_t)irq11, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(44, (uint64_t)irq12, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(45, (uint64_t)irq13, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(46, (uint64_t)irq14, GDT_CODE_SEG, INTERRUPT_GATE); + add_to_idt(47, (uint64_t)irq15, GDT_CODE_SEG, INTERRUPT_GATE); +} + +void init_idt() +{ + init_idt_table(); + idt_pointer.size = sizeof(idt_entry) * 256 - 1; + idt_pointer.offset = (uint64_t)&idt_table; + + remap_pic(); + + load_idt(&idt_pointer); +} diff --git a/kernel/src/cpu/io.c b/kernel/src/cpu/io.c new file mode 100644 index 0000000..6bf67d0 --- /dev/null +++ b/kernel/src/cpu/io.c @@ -0,0 +1,13 @@ +#include + +uint8_t inb(uint32_t port) +{ + uint8_t ret; + __asm__ volatile ("inb %%dx, %%al" : "=a"(ret) : "d"(port)); + return ret; +} + +void outb(uint32_t port, uint8_t value) +{ + __asm__ volatile ("outb %%al, %%dx" : : "d"(port), "a"(value)); +} diff --git a/kernel/src/cpu/irq.c b/kernel/src/cpu/irq.c new file mode 100644 index 0000000..1e02f23 --- /dev/null +++ b/kernel/src/cpu/irq.c @@ -0,0 +1,289 @@ +#include +#include +#include +#include +#include + +char* exception_name[] = { + "Divide-by-zero Error", + "Debug", + "Non-maskable Interrupt", + "Breakpoint", + "Overflow", + "Bound Range Exceeded", + "Invalid Opcode", + "Device Not Available", + "Double Fault", + "Coprocessor Segment Overrun", + "Invalid TSS", + "Segment Not Present", + "Stack-Segment Fault", + "General Protection Fault", + "Page Fault", + "Reserved", + "x87 Floating-Point Exception", + "Alignment Check", + "Machine Check", + "SIMD Floating-Point Exception", + "Virtualization Exception", + "Control Protection Exception", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Hypervisor Injection Exception", + "VMM Communication Exception", + "Security Exception", + "Reserved", +}; + +void isr0_handler(void) +{ + fb_draw_string(fb, exception_name[0], 0, 0, WHITE, BLACK); +} + +void isr1_handler(void) +{ + fb_draw_string(fb, exception_name[1], 0, 0, WHITE, BLACK); +} + +void isr2_handler(void) +{ + fb_draw_string(fb, exception_name[2], 0, 0, WHITE, BLACK); +} + +void isr3_handler(void) +{ + fb_draw_string(fb, exception_name[3], 0, 0, WHITE, BLACK); +} + +void isr4_handler(void) +{ + fb_draw_string(fb, exception_name[4], 0, 0, WHITE, BLACK); +} + +void isr5_handler(void) +{ + fb_draw_string(fb, exception_name[5], 0, 0, WHITE, BLACK); +} + +void isr6_handler(void) +{ + fb_draw_string(fb, exception_name[6], 0, 0, WHITE, BLACK); +} + +void isr7_handler(void) +{ + fb_draw_string(fb, exception_name[7], 0, 0, WHITE, BLACK); +} + +void isr8_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[8], 0, 0, WHITE, BLACK); +} + +void isr9_handler(void) +{ + fb_draw_string(fb, exception_name[9], 0, 0, WHITE, BLACK); +} + +void isr10_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[10], 0, 0, WHITE, BLACK); +} + +void isr11_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[11], 0, 0, WHITE, BLACK); +} + +void isr12_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[12], 0, 0, WHITE, BLACK); +} + +void isr13_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[13], 0, 0, WHITE, BLACK); +} + +void isr14_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[14], 0, 0, WHITE, BLACK); +} + +void isr15_handler(void) +{ + fb_draw_string(fb, exception_name[15], 0, 0, WHITE, BLACK); +} + +void isr16_handler(void) +{ + fb_draw_string(fb, exception_name[16], 0, 0, WHITE, BLACK); +} + +void isr17_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[17], 0, 0, WHITE, BLACK); +} + +void isr18_handler(void) +{ + fb_draw_string(fb, exception_name[18], 0, 0, WHITE, BLACK); +} + +void isr19_handler(void) +{ + fb_draw_string(fb, exception_name[19], 0, 0, WHITE, BLACK); +} + +void isr20_handler(void) +{ + fb_draw_string(fb, exception_name[20], 0, 0, WHITE, BLACK); +} + +void isr21_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[21], 0, 0, WHITE, BLACK); +} + +void isr22_handler(void) +{ + fb_draw_string(fb, exception_name[22], 0, 0, WHITE, BLACK); +} + +void isr23_handler(void) +{ + fb_draw_string(fb, exception_name[23], 0, 0, WHITE, BLACK); +} + +void isr24_handler(void) +{ + fb_draw_string(fb, exception_name[24], 0, 0, WHITE, BLACK); +} + +void isr25_handler(void) +{ + fb_draw_string(fb, exception_name[25], 0, 0, WHITE, BLACK); +} + +void isr26_handler(void) +{ + fb_draw_string(fb, exception_name[26], 0, 0, WHITE, BLACK); +} + +void isr27_handler(void) +{ + fb_draw_string(fb, exception_name[27], 0, 0, WHITE, BLACK); +} + +void isr28_handler(void) +{ + fb_draw_string(fb, exception_name[28], 0, 0, WHITE, BLACK); +} + +void isr29_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[29], 0, 0, WHITE, BLACK); +} + +void isr30_handler(uint64_t error) +{ + fb_draw_string(fb, exception_name[30], 0, 0, WHITE, BLACK); +} + +void isr31_handler(void) +{ + fb_draw_string(fb, exception_name[31], 0, 0, WHITE, BLACK); +} + +void irq0_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); +} + +void irq1_handler(void) +{ + keyboard_handler(); + outb(PIC1_COMMAND, PIC_EOI); +} + +void irq2_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); +} + +void irq3_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); +} + +void irq4_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); +} + +void irq5_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); +} + +void irq6_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); +} + +void irq7_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); +} + +void irq8_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); + outb(PIC2_COMMAND, PIC_EOI); +} + +void irq9_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); + outb(PIC2_COMMAND, PIC_EOI); +} + +void irq10_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); + outb(PIC2_COMMAND, PIC_EOI); +} + +void irq11_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); + outb(PIC2_COMMAND, PIC_EOI); +} + +void irq12_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); + outb(PIC2_COMMAND, PIC_EOI); +} + +void irq13_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); + outb(PIC2_COMMAND, PIC_EOI); +} + +void irq14_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); + outb(PIC2_COMMAND, PIC_EOI); +} + +void irq15_handler(void) +{ + outb(PIC1_COMMAND, PIC_EOI); + outb(PIC2_COMMAND, PIC_EOI); +} diff --git a/kernel/src/cpu/irq_stub.S b/kernel/src/cpu/irq_stub.S new file mode 100644 index 0000000..ddd197a --- /dev/null +++ b/kernel/src/cpu/irq_stub.S @@ -0,0 +1,108 @@ +.macro pushall + push %rax + push %rcx + push %rdx + push %rsi + push %rdi + push %r8 + push %r9 + push %r10 + push %r11 + pushfq +.endm + +.macro popall + popfq + pop %r11 + pop %r10 + pop %r9 + pop %r8 + pop %rdi + pop %rsi + pop %rdx + pop %rcx + pop %rax +.endm + + +.macro isr_no_error number +.global isr\number +isr\number: + pushall + cld + call isr\number\()_handler + popall + iretq +.endm + +.macro isr_error number +.global isr\number +isr\number: + # rdi not saved + pop %rdi + pushall + cld + call isr\number\()_handler + popall + iretq +.endm + +isr_no_error 0 +isr_no_error 1 +isr_no_error 2 +isr_no_error 3 +isr_no_error 4 +isr_no_error 5 +isr_no_error 6 +isr_no_error 7 +isr_error 8 +isr_no_error 9 +isr_error 10 +isr_error 11 +isr_error 12 +isr_error 13 +isr_error 14 +isr_no_error 15 +isr_no_error 16 +isr_error 17 +isr_no_error 18 +isr_no_error 19 +isr_no_error 20 +isr_no_error 21 +isr_no_error 22 +isr_no_error 23 +isr_no_error 24 +isr_no_error 25 +isr_no_error 26 +isr_no_error 27 +isr_no_error 28 +isr_error 29 +isr_error 30 +isr_no_error 31 + +.macro irq number +.global irq\number +irq\number: + pushall + cld + call irq\number\()_handler + popall + iretq +.endm + +irq 0 +irq 1 +irq 2 +irq 3 +irq 4 +irq 5 +irq 6 +irq 7 +irq 8 +irq 9 +irq 10 +irq 11 +irq 12 +irq 13 +irq 14 +irq 15 diff --git a/kernel/src/cpu/pic.c b/kernel/src/cpu/pic.c new file mode 100644 index 0000000..801556d --- /dev/null +++ b/kernel/src/cpu/pic.c @@ -0,0 +1,24 @@ +#include +#include + +void remap_pic(void) +{ + // save masks +// uint8_t a1 = inb(PIC1_DATA); +// uint8_t a2 = inb(PIC2_DATA); + + // starts the initialization sequence (in cascade mode) + outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4); + outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4); + outb(PIC1_DATA, 0x20); // ICW2: Master PIC vector offset + outb(PIC2_DATA, 0x28); // ICW2: Slave PIC vector offset + outb(PIC1_DATA, 4); // ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100) + outb(PIC2_DATA, 2); // ICW3: tell Slave PIC its cascade identity (0000 0010) + + outb(PIC1_DATA, ICW4_8086); + outb(PIC2_DATA, ICW4_8086); + + // mask interrupts + outb(PIC1_DATA, 0xfd); + outb(PIC2_DATA, 0xff); +} -- cgit v1.2.3